1. Field of the Invention
The present invention relates generally to methods of manufacturing semiconductor devices. More particularly, the present invention relates to tape-based methods of manufacturing semiconductor devices having so-called ball grid array connection patterns for electrically connecting a semiconductor die to an external device (e.g., a printed circuit board). The present invention also relates to so-called ball grid array (BGA) semiconductor device packages formed in accordance with the disclosed methods.
2. Background of the Related Art
The dimensions of electronic devices are ever-decreasing. Consequently, alternative methods of semiconductor device assembly and packaging are continually being provided to reduce the effective size of such devices. One such method provides for a decrease in the size of the “footprint” of the semiconductor device on higher-level packaging, substrates, or carrier substrates, such as printed circuit boards (PCBs) or printed wiring boards (PWBs). Semiconductor devices having grid array connection patterns are being fabricated with increasing frequency, as the manner in which such devices are electrically connected to carrier substrates reduces the surface area consumed by such devices on the carrier substrates to an area the same as, or only slightly larger than, the device dimensions. Semiconductor devices with grid array connection patterns, including BGA semiconductor device packages, provide improved surface mountability and greater package density as well.
Flip-chip semiconductor device packages are known in the art and, in general, include a semiconductor die having an active surface with bond pads thereon. An insulative layer, which may be formed of a resin material, is placed or deposited on the active surface of the semiconductor die and includes openings therein to expose the bond pads of the semiconductor die. Conductive traces in the form of a so-called “redistribution layer” (RDL) are patterned on the insulative layer in contact with the bond pads and solder balls or other electrically discrete conductive elements are placed at the ends of the traces opposite the bond pads on the top of the insulative layer. While the resulting semiconductor device is extremely compact, it is also somewhat delicate as the semiconductor die itself must be handled, rather than a supporting substrate.
It is known to fabricate a BGA package using a polymer substrate carrying conductive traces in the form of leads extending over a slot in the center thereof and adhesively bonded to the active surface of a semiconductor die, as disclosed in U.S. Pat. No. 6,310,390 to Moden, assigned to the assignee of the present invention. The bond pads on the semiconductor die may be connected to the cantilevered lead ends extending over the slot by thermocompression bonding and the leads may communicate signals from the wires to discrete conductive elements in the form of solder balls. By way of example, the layer may be formed of a polymer film element which may be adhered and cut from a larger film after the semiconductor die and others adhered to the film are otherwise assembled.
Several disadvantages to such packaging methods and semiconductor packages so assembled have been recognized. For instance, BGA semiconductor device packages manufactured by such a method are not structurally reinforced and, thus, may be difficult to handle. As a result, some manufacturing processes provide for structural reinforcement by providing a support layer on the bottom surface of the semiconductor die. These methods, however, increase the vertical profile of the devices, which is undesirable. A further disadvantage of typical BGA packages is poor heat dissipation and/or management. Failure to adequately manage heat may result in premature failure of the semiconductor device.
Various attempts have been made to overcome these difficulties. One such attempt is presented in U.S. Pat. No. 6,300,165 B2 to Castro (hereinafter the “'165 patent”), the disclosure of which is hereby incorporated herein by this reference as if set forth in its entirety herein. The '165 patent teaches an integrated circuit (semiconductor die) package substrate for use with a ball grid array, and method of manufacturing the same, wherein circuitry-bearing decals are applied directly to a rather large metal heat sink. The heat sink has a dielectric layer formed directly on a bottom surface thereof. A circuit pattern which will accommodate a ball grid array is formed on the dielectric layer. A plurality of these package substrates are formed adjacent one another and are supplied in the form of a lead frame segment. A single segment, on its dielectric layer, contains all of the circuitry desiredfor a series of semiconductor packages. Preferably, the segment is applied to multiple integrated circuit devices in succession in a width-wise, or transverse, direction with respect to the longitudinal axis of the segment. Subsequently, electrical connections are secured and the tape is cut at separation indicators located between the devices. The individual units are then singulated from the segment by conventional trim and form techniques and the segment is subject to a final cutting operation in which the lead frame rails are removed.
While the ball grid array substrate of the '165 patent provides improved rigidity and heat management, it has a number of drawbacks. For instance, since the circuitry-bearing dielectric layer of the '165 patent is secured directly to the heat sink, a polyimide PWB panel must be fabricated to carry the circuit traces. Fabrication requires milling and/or drilling of a wire bond slot, as well as tooling holes and alignment fiducials. Further, during singulation of the integrated circuit packages, either end milling or punch tooling must be used. Such additional process steps are undesirable. Additionally, machine placement of the segment on a series of semiconductor devices in this manner permits accuracies of only ±100 μm. This is somewhat undesirable as bond pads on semiconductor devices are often separated only by this degree of error and, thus, wire bond connections to the bond pads must be individually inspected for accuracy of wire bond placement. Further, the method of the '165 patent is a rather slow process, thus affecting throughput goals.
Another attempt at producing an improved BGA semiconductor device package provided in U.S. Pat. No. 6,268,650 B1 to Kinsman et al. (hereinafter the “'650 patent”), the disclosure of which is hereby incorporated herein by this reference as if set forth in its entirety herein. The '650 patent teaches a semiconductor package formed of a semiconductor die having an electrically conductive layer and an insulating layer thereon which supports a ball grid array substrate. The conductive layer is formed of metal which provides structural support (stiffness) and also acts as a heat sink dissipating heat away from the die. An adhesive layer may be placed between the active surface of the die and the conductive layer to adhere the conductive layer to the semiconductor die. The ball grid array substrate is electrically connected to the die by wires, traces, and/or other conductive elements as known in the art. Additionally, one or more of the conductive elements may be connected to the conductive layer enabling the conductive layer to be used as a ground plane for the device.
A plurality of semiconductor packages of the '650 patent may be formed by a tape-based process and subsequently separated from one another. The tape structure, in one embodiment, is of an indefinite length and includes an upper insulating layer and a lower conductive metal layer. A single tape segment, on its insulating layer, contains all of the circuitry desired for a series of semiconductor packages and is preferably applied to multiple semiconductor devices in succession in a widthwise, or transverse, direction to the longitudinal extent of the tape segment. Subsequently, electrical connections accommodating a grid array connection pattern may be secured to the semiconductor die and the tape may be cut at separation indicators located between the devices to separate the individual packages from one another.
Semiconductor packages manufactured by the methods of the '650 patent provide improved rigidity and heat management relative to conventional BGA packages. However, this approach has certain drawbacks as well. For instance, because a single tape segment contains all of the circuitry desired for each of a series of semiconductor devices, machine placement thereof provides accuracies only within the same margin of error as the method of the '165 patent (i.e., ±100 μm). Again, this is undesirable, as bond pads are often separated only by this degree of error and, as such, wire bond connections to bond pads must be individually inspected for accuracy.
Upon consideration of the above-described state of the art, the inventor has recognized that a method of applying circuitry-bearing tape segments to the active surface of a semiconductor die which offers a placement accuracy statistically improved over ±100 μm would be desirable. Further, the inventor has recognized that a method of fabricating semiconductor devices using conventional lead frame attach equipment (e.g., leads-over-chip (LOC) and lead lock tape assembly equipment) to attach circuitry-bearing tape segments to the active surface of a semiconductor device would provide enhanced placement accuracy and associated higher yield. Further, the resulting semiconductor devices would exhibit improved thermal, electrical and rigidity properties over the current state of the art.